Demands for high-speed data processing and communication continue to push the electronics industry to develop faster and higher functioning circuits, as has been realized in very-large-scale integration of circuits on small areas of silicon wafer. Technologies such as telecommunications and networking, for example, continue to fuel research and design efforts that facilitate serial data rate capabilities on the order of hundreds of gigabits per second and higher.
Such data-processing speeds are defined relative to a clock source that provides one or more high-frequency signals to circuits (and/or functionally-defined circuit modules) that advance through their designed (logic) states in order to perform their designed operation. In a typical application, the clock source provides a high-frequency signal that is processed through divider circuits to generate reduced-frequency clock signals used by the respective logic circuits to advance through their logic states at the appropriate rate. Thus, these data-processing speeds (or data rates) are increased mainly by the clock source, and related divider circuits.
This increase in signal frequency also increases noise, such as clock jitter, created by these circuits. Clock jitter refers to the deviation in a clock signals actual transition in time from its ideal position in time, where the signals actual transition may either lag or lead the ideal position in time. Clock jitter includes cycle-to-cycle jitter, which is the change in a signal's output transition from its corresponding position in the previous cycle, as well as period jitter, which is the maximum change in a signal's output transition from its ideal position. Since both forms of jitter are present in high-frequency clocks, the circuit designer attempting to achieve a maximum data rate would typically need to account for the short-term and long-term (accumulation of such jitter over time) effects of clock jitter.
Design specifications often define a data rate capability as well as a total jitter budget. For example, an Optical Carrier (OC)-192 compliant transceiver may have a data rate capability of 10 gigabits per second (Gbps) and may be allowed less than 1 picosecond (ps) of total jitter due to random noise. Further, only 10 ps is allowed for deterministic jitter. Because clock-signal divider circuits are often used, duplicated and distributed throughout such circuits, errors emanating from the accumulation of such jitter can significantly interfere with system performance and reliability. Therefore, predicting and reducing jitter induced by all significant sources, such as divider circuits that distribute clock signals, is important in such applications.
The potential effects of jitter in connection with such high frequency clock signals can be present in a wide variety of circuits including those implemented as functionally-defined modules, stand-alone chips or in combination with other circuit arrangements (e.g., systems or subsystems). In highly-integrated circuits, the proximity of the circuitry can increase the effects of clock jitter. Programmable devices, whether mask programmable or field programmable, are a class of highly-integrated circuits that, when configured for such high-speed data processing/transmission applications, can accentuate concerns for exceeding expected levels of normal jitter or a specification-defined jitter budget.
The field-programmable nature of FPGAs (field programmable gate array), for example, permits such a wide variance of circuit-design possibilities that the accumulated jitter in the ultimate design can be overlooked or underestimated. FPGAs may be user-programmed to perform a wide variety of functions including high-frequency clock processing (and its inherent clock distribution). Since FPGAs have become very popular for telecommunication applications, Internet applications, and switching and routing applications, all of which involve high-frequency clock processing, this concern has become increasingly important.
Certain high-frequency clock processing circuits are more likely to induce clock jitter. Clock divider circuits that include a divisor fraction, fall into this category. For instance, one type of existing circuit that performs fractional divisions uses logic circuitry that alternates between two integer divide ratios so that the average is the desired value. For example, to divide by 16 ½, the divider circuit would alternately divide using the two nearest integers as divisors (dividing by 16, by 17, by 16, and so on), so that the average divisor is 16½. The output of this divider circuit carries high levels of jitter.
Another type of divider circuit inverts the phase of the input clock for each cycle. For example, such a circuit performing a 1/division ( 21/2, 4½, 8½, etc.) inverts the signal to flip the phase of the input clock by 180 degrees after another decode portion of the divider indicates that the divide-by-N operation is complete. Although its output carries lower levels of measurable jitter, the circuit places a high load on the source circuit's high-speed signal being divided. This method also has timing problems in generating the phase control signal for the high-speed clock.
Accordingly, an approach that addresses the aforementioned problems, as well as other related problems, is desirable.